1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device where MOS logic circuits and bipolar logic circuits are mixed.
2. Description of the Related Art
Recently, in a high speed logic large scale integrated (LSI) circuit, particularly, in a communication LSI circuit, bipolar circuits such as emitter coupled logic (ECL) circuits having high speed characteristics and high load characteristics and complementary metal oxide semiconductor (CMOS) circuits (or bipolar CMOS (BiCMOS)) having a low power consumption and a high manufacturing yield are constructed on the same chip to thereby improve the performance of a system.
In a first prior art semiconductor device where a CMOS circuit and an ECL circuit are mixed, the CMOS circuit is operated between a positive power supply voltage V.sub.DD and a ground voltage GND, and the ECL circuit is operated between the ground voltage GND and a negative power supply voltage V.sub.EE. This will be explained later in detail.
In the first prior art semiconductor device, however. since the difference between CMOS logic signals and ECL logic signals is large, the number of elements of level conversion circuits is increased, and also, a time required for such a level conversion is increased.
In a second prior art semiconductor device where a CMOS circuit and an ECL circuit are mixed, the CMOS circuit is also operated between the ground voltage GND and the negative power supply voltage V.sub.EE in the same way as the ECL circuit (see JP-A-SHO62-214655). This will be also explained later in detail.
In the second prior art semiconductor device, however, since the CMOS circuit is operated based upon the power supply voltage V.sub.EE (precisely, -5.2 V or -4.5 V), the elements of the CMOS circuit are deteriorated in reliability, and the duration of gate insulating layers thereof is also deteriorated.